Field
Apparatus and methods consistent with exemplary embodiments relate to time signal processing.
Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “signal,” “circuit,” “logical signal,” “clock,” “trip point,” “inverter,” “buffer,” “circuit node,” “finite state machine,” “data flip-flop,” “multiplexer,” “MOS (metal oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “CMOS (complementary metal oxide semiconductor),” “transistor,” “source,” “gate,” “drain,” and “CMOS inverter.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.
Through this disclosure, a logical signal is a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal. A logical signal is embodied by a voltage; the logical signal is “high” (“low”) when the voltage is above (below) an associated trip point of a recipient logical device that receives and processes the logical signal. For brevity, the associated trip point is simply referred to as the trip point of the logical signal. In this disclosure, the trip point of a first logical signal may not be necessarily the same as the trip point of a second logical signal.
If a logical signal is “high” (or “1”) it is said to be “asserted.” If the logical signal is “low,” it is said to be “de-asserted.”
A clock signal is a periodic logical signal.
A logical signal exhibits a rising (falling) edge when the logical signal undergoes a low-to-high (high-to-low) transition.
A time signal may include two constituent logical signals, including a first logical signal (denoted by a suffix “+” in a subscript) and a second logical signal (denoted by a suffix “−” in a subscript). The value of the time signal may include a time difference between the second logical and the first logical signal. For example, a time signal X may include two constituent logical signals X+ and X−, wherein X+ has a rising edge at time t+ and X− has a rising edge at time t−. A value of the time signal is t−−t+.
A time shifter receives a time signal X and outputs an another time signal X′ such that a value of the time signal X′ is the same as a value of the time signal X. FIG. 1 shows a time shifter 100 including a first buffer 100P and a second buffer 100N. The time signal X includes two constituent logical signals X′+ and X′−, while the time signal X′ includes two constituent logical signals X′+ and X′−. A buffer preserves a value of a signal but introduces a delay. Therefore, X′+ is the same as X+ except for a delay determined by the first buffer 100P. Likewise, X′− is the same as X− except for a delay determined by the second buffer 100N. As long as the first buffer 100P is substantially identical to the second buffer 100N, those of ordinary skill in the art can also recognize that a value of the time signal X′ will be the same as a value of the time signal X. A time signal can be processed in various operations. For instance, a time signal can be amplified (using a time amplifier), and also can be quantized (using a time-to-digital converter). A time shifter allows a time signal to be processed at a later time. In many cases, it is desired that a time signal can be processed at a later time in accordance with a system clock. Using time shifter 100 of FIG. 1 can allow a time signal to be processed at a later time in accordance with a system clock, but only in an ad hoc manner, wherein a timing of the time signal relative to the system clock is pre-known to some extent. In this situation, a workable buffer can be chosen with pre-knowledge of the time signal relative to a system clock. A conventional time shifter is described in Hong et al., “A 0.004 mm2 250 μW ΔΣ TDC with time-difference accumulator and a 0.012 mm2 2.5 mW bang-bang digital PLL using PRNG for low-power SoC applications,” presented in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp. 240-242.
Apparatus and methods consistent with an inventive concept relate to a systematic way of shifting a time signal so as to be compatible with a system clock.